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low capacitance, low charge injection, 15 v/+12 v i cmos quad spst switches adg1211/adg1212/adg1213 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2009 analog devices, inc. all rights reserved. features 1 pf off capacitance 2.6 pf on capacitance <1 pc charge injection 33 v supply range 120 on resistance fully specified at 15 v, +12 v no v l supply required 3 v logic-compatible inputs rail-to-rail operation 16-lead tssop and 16-lead lfcsp typical power consumption: <0.03 w applications automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems audio signal routing video signal routing communication systems general description the adg1211/adg1212/adg1213 are monolithic complemen- tary metal-oxide semiconductor (cmos) devices containing four independently selectable switches designed on an i cmos? (industrial cmos) process. i cmos is a modular manufacturing process combining high voltage cmos and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no previous generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. the ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching. functional block diagram in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1211 switches shown for a logic 1 input in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1212 in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg1213 04778-001 figure 1. i cmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. the adg1211/adg1212/adg1213 contain four independent single-pole/single-throw (spst) switches. the adg1211 and adg1212 differ only in that the digital control logic is inverted. the adg1211 switches are turned on with logic 0 on the appropriate control input, while logic 1 is required for the adg1212. the adg1213 has two switches with digital control logic similar to that of the adg1211; the logic is inverted on the other two switches. the adg1213 exhibits break-before- make switching action for use in multiplexer applications. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. product highlights 1. ultralow capacitance. 2. <1 pc charge injection. 3. 3 v logic-compatible digital inputs: v ih = 2.0 v, v il = 0.8 v. 4. no v l logic power supply required. 5. ultralow power dissipation: <0.03 w. 6. 16-lead tssop and 3 mm 3 mm lfcsp packages.
adg1211/adg1212/adg1213 rev. a | page 2 of 16 table of contents specifications ..................................................................................... 3 ? dual supply ................................................................................... 3 ? single supply ................................................................................. 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? te r m i no l o g y .......................................................................................8 ? typical performance characteristics ..............................................9 ? te s t c i rc u it s ..................................................................................... 12 ? outline dimensions ....................................................................... 14 ? ordering guide .......................................................................... 15 ? revision history 2/09rev. 0 to rev. a changes to power requirements, i dd , digital inputs = 5 v parameter, table 1 ............................................................................. 4 changes to power requirements, i dd , digital inputs = 5 v parameter, table 2 ............................................................................. 5 7/05revision 0: initial version
adg1211/adg1212/adg1213 rev. a | page 3 of 16 specifications dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. y version 1 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance (r on ) 120 typ v s = 10 v, i s = ?1 ma; see figure 20 190 230 260 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels (?r on ) 2.5 typ v s = 10 v, i s = ?1 ma 6 10 11 max on resistance flatness (r flat(on) ) 20 typ v s = ?5 v/0 v/+5 v; i s = ?1 ma 57 72 79 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0.02 na typ v s = 10 v, v d = ? 10 v; see figure 21 0.1 0.6 1 na max drain off leakage, i d (off) 0.02 na typ v s = 10 v, v d = ? 10 v; see figure 21 0.1 0.6 1 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 10 v; see figure 22 0.1 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0 . 1 a m a x digital input capacitance, c in 2.5 pf typ dynamic characteristics 2 t on 105 ns typ r l = 300 , c l = 35 pf 125 160 185 ns max v s = 10 v; see figure 23 t off 40 ns typ r l = 300 , c l = 35 pf 50 60 60 ns max v s = 10 v; see figure 23 break-before-make time delay, t d 25 ns typ r l = 300 , c l = 35 pf (adg1213 only) 10 ns min v s1 = v s2 = 10 v; see figure 24 charge injection ?0.3 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 25 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 total harmonic distortion + noise 0.15 % typ r l = 10 k, 5 v rms, f = 20 hz to 20 khz ?3 db bandwidth 1000 mhz typ r l = 50 , c l = 5 pf; see figure 28 c s (off) 0.9 pf typ v s = 0 v, f = 1 mhz 1.1 pf max v s = 0 v, f = 1 mhz c d (off) 1 pf typ v s = 0 v, f = 1 mhz 1.2 pf max v s = 0 v, f = 1 mhz c d , c s (on) 2.6 pf typ v s = 0 v, f = 1 mhz 3 pf max v s = 0 v, f = 1 mhz
adg1211/adg1212/adg1213 rev. a | page 4 of 16 y version 1 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 v 380 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i ss 0.001 a typ digital inputs = 5 v 1.0 a max 1 temperature range for y version is ? 40c to +125c. 2 guaranteed by design, not subject to production test.
adg1211/adg1212/adg1213 rev. a | page 5 of 16 single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. y version 1 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 300 typ v s = 0 v to 10 v, i s = ?1 ma; see figure 20 475 567 625 max v dd = 10.8 v, v ss = 0 v on resistance match between channels (?r on ) 4.5 typ v s = 0 v to 10 v, i s = ?1 ma 12 26 27 max on resistance flatness (r flat(on) ) 60 typ v s = 3 v/6 v/9 v, i s = ?1 ma leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 21 0.1 0.6 1 na max drain off leakage, i d (off) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 21 0.1 0.6 1 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 1 v or 10 v; see figure 22 0.1 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ v in = v inl or v inh 0 . 1 a m a x digital input capacitance, c in 3 pf typ dynamic characteristics 2 t on 120 ns typ r l = 300 , c l = 35 pf 155 190 225 ns max v s = 8 v; see figure 23 t off 45 ns typ r l = 300 , c l = 35 pf 65 75 85 ns max v s = 8 v; see figure 23 break-before-make time delay, t d 50 ns typ r l = 300 , c l = 35 pf (adg1213 only) 10 ns min v s1 = v s2 = 8 v; see figure 24 charge injection 0 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 25 off isolation 80 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 ?3 db bandwidth 900 mhz typ r l = 50 , c l = 5 pf; see figure 28 c s (off) 1.2 pf typ v s = 6 v, f = 1 mhz 1.4 pf max v s = 6 v, f = 1 mhz c d (off) 1.3 pf typ v s = 6 v, f = 1 mhz 1.5 pf max v s = 6 v, f = 1 mhz c d , c s (on) 3.2 pf typ v s = 6 v, f = 1 mhz 3.9 pf max v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 v 380 a max 1 temperature range for y version is ? 40c to +125c. 2 guaranteed by design, not subject to production test.
adg1211/adg1212/adg1213 rev. a | page 6 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs 1 v ss C 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 gnd C 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current per channel, s or d 25 ma operating temperature range automotive (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 16-lead tssop, ja thermal impedance (4-layer board) 112c/w 16-lead lfcsp, ja thermal impedance 72.7c/w reflow soldering peak temperature, pb free 260c 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. table 4. adg1211/adg1212 truth table adg1211 inx adg1212 inx switch condition 0 1 on 1 0 off table 5. adg1213 truth table adg1213 inx switch 1, 4 switch 2, 3 0 off on 1 on off esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adg1211/adg1212/adg1213 rev. a | page 7 of 16 pin configurations and function descriptions top view 1 2 3 4 5 6 7 8 adg1211/ adg1212/ adg1213 nc = no connect 16 15 14 13 12 11 10 9 d1 s1 v ss d4 s4 gnd in1 d2 s2 v dd d3 in4 in3 s3 nc in2 04788-002 figure 2. tssop pin configuration pin 1 indicator nc = no connect notes 1. exposed pad tied to substrate, v ss . 1s1 2v ss 3gnd 4s4 11 v dd 12 s2 10 nc 9s3 5 d 4 6 i n 4 7 i n 3 8 d 3 1 5 i n 1 1 6 d 1 1 4 i n 2 1 3 d 2 top view (not to scale) 04778-003 adg1211/adg1212/adg1213 figure 3. lfcsp pin configuration table 6. pin function descriptions pin no. mnemonic description tssop lfcsp 1 15 in1 logic control input. 2 16 d1 drain terminal. can be an input or output. 3 1 s1 source terminal. can be an input or output. 4 2 v ss most negative power supply potential. 5 3 gnd ground (0 v) reference. 6 4 s4 source terminal. can be an input or output. 7 5 d4 drain terminal. can be an input or output. 8 6 in4 logic control input. 9 7 in3 logic control input. 10 8 d3 drain terminal. can be an input or output. 11 9 s3 source terminal. can be an input or output. 12 10 nc no connection. 13 11 v dd most positive power supply potential. 14 12 s2 source terminal. can be an input or output. 15 13 d2 drain terminal. can be an input or output. 16 14 in2 logic control input.
adg1211/adg1212/adg1213 rev. a | page 8 of 16 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminals d and s. r on the ohmic resistance between d and s. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, measured with reference to ground. c d (off) the off switch drain capacitance, measured with reference to ground. c d , c s (on) the on switch capacitance, measured with reference to ground. c in the digital input capacitance. t on the delay between applying the digital control input and the output switching on. see figure 23 . t off the delay between applying the digital control input and the output switching off. see figure 23 . charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. thd + n the ratio of the harmonic amplitude plus noise of the signal to the fundamental.
adg1211/adg1212/adg1213 rev. a | page 9 of 16 typical performance characteristics v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v source or drain voltage (v) on resistance ( ) 200 180 160 140 120 100 60 80 0 20 40 ?18 ?15 ?12 ?9 ?6 ?3 3 9 15 0 6 12 18 04778-008 v dd = +13.5v v ss = ?13.5v t a = +25 c figure 4. on resistance as a function of v d (v s ) for dual supply source or drain voltage (v) on resistance ( ) 450 400 350 300 250 150 200 0 50 100 ?5 ?4 ?3 ?2 ?1 2 4 01 3 5 04778-004 v dd = +5.5v v ss = ?5.5v t a = +25 c figure 5. on resistance as a function of v d (v s ) for dual supply v dd = 13.2v v ss = 0v source or drain voltage (v) on resistance ( ) 450 400 350 300 250 150 200 0 50 100 024681012 04778-005 v dd = 12v v ss = 0v v dd = 10.8v v ss = 0v t a = 25 c figure 6. on resistance as a function of v d (v s ) for single supply source or drain voltage (v) on resistance ( ) 250 150 200 0 50 100 ?15 ?10 ?5 0 5 10 15 04778-006 v dd = +15v v ss = ?15v t a = +125 c t a = +25 c t a = +85 c t a = ?40 c figure 7. on resistance as a function of v d (v s ) for different temperatures, dual supply source or drain voltage (v) on resistance ( ) 600 400 500 300 200 0 100 02468101 04778-007 2 v dd = +12v v ss = 0v t a = +125 c t a = +25 c t a = +85 c t a = ?40 c figure 8. on resistance as a function of v d (v s ) for different temperatures, single supply temperature (c) leakage (na) 0.20 0.15 0.10 0.05 0 ?0.10 ?0.05 ?0.15 ?0.20 20 0 40 60 80 100 120 04778-012 i s (off) i d (off) i d , i s (on) v dd = +15v v ss = ?15v v bias = +10v/?10v figure 9. leakage currents as a function of temperature, dual supply
adg1211/adg1212/adg1213 rev. a | page 10 of 16 temperature (c) leakage (na) 0.30 0.25 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 20 0 40 60 80 100 120 04778-013 i s (off) i d (off) i d , i s (on) v dd = 12v v ss = 0v v bias = 1v/10v figure 10. leakage currents as a function of temperature, single supply logic, in x (v) i dd ( a) 60 50 40 30 10 20 0 0 2 4 6 8 10 12 14 04778-011 v dd = +12v, v ss = 0v v dd = +15v, v ss = ?15v i dd per channel t a = +25 c figure 11. i dd vs. logic level v s (v) charge injection (pc) 6 4 2 0 ?4 ?2 ?6 ?15 ?10 ?5 0 5 10 15 04778-015 v dd = +12v, v ss = 0v v dd = +5v, v ss = ?5v v dd = +15v, v ss = ?15v source to drain drain to source t a = +25 c figure 12. charge injection vs. source voltage temperature (c) time (ns) 200 160 180 140 100 60 20 120 80 40 0 ?40 ?20 40200 60 80 100 120 04778-016 15v ds t off 12v ss t off 15v ds t on 12v ss t on figure 13. t on /t off times vs. temperature frequency (hz) off isolation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 100k 1m 10m 100m 1g 04778-017 v dd = +15v v ss = ?15v t a = +25 c figure 14. off isolation vs. frequency frequency (hz) crosstalk (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?120 ?110 10k 100k 1m 10m 100m 04778-018 v dd = +15v v ss = ?15v t a = +25 c figure 15. crosstalk vs. frequency
adg1211/adg1212/adg1213 rev. a | page 11 of 16 frequency (hz) attenuatioin (db) 0 ?10 ?5 ?15 ?25 ?20 ?30 10k 100k 1m 10m 1g 100m 10g 04778-019 v dd = +15v v ss = ?15v t a = +25 c figure 16. on response vs. frequency frequency (hz) thd+n (%) 10.00 1.00 0.10 0.01 10 100 1k 10k 100k 04778-029 load = +10k t a = +25 c v dd = +5v, v ss = ?5v, v s = +3.5vrms v dd = +15v, v ss = ?15v, v s = +5vrms figure 17. thd + n vs. frequency v bias (v) capacitance (pf) 3.0 2.5 2.0 1.5 1.0 0.5 ?10?8?6?4?20246810 04778-031 v dd = +15v v ss = ?15v t a = +25 c source/drain on source off drain off figure 18. capacitance vs. source voltage, dual supply v bias (v) capacitance (pf) 4.0 3.0 3.5 1.5 2.0 2.5 1.0 0.5 0 024 68101 04778-030 2 v dd = 12v v ss = 0v t a = 25 c source/drain on source off drain off figure 19. capacitance vs. source voltage, single supply
adg1211/adg1212/adg1213 rev. a | page 12 of 16 test circuits i ds v1 sd v s r on = v1/i ds 04778-020 sd v s a a v d i s (off) i d (off) 04778-021 sd a v d i d (on) nc nc = no connect 04778-022 figure 20. on resistance figure 21. off leakage figure 22. on leakage v s in sd gnd r l 300 c l 35pf v out v dd v ss 0.1 f v dd 0.1 f v ss adg1212 adg1211 v in v in v out t on t off 50% 50% 90% 90% 50% 50% 04778-023 figure 23. switching times v s2 in1, in2 s2 d2 v s1 s1 d1 gnd r l 300 c l 35pf v out2 v out1 v dd v ss 0.1 f v dd 0.1 f v ss v in v out1 v out2 adg1213 t d t d 50% 50% 90% 90% 90% 90% 0v 0v 0v r l 300 c l 35pf 04778-024 figure 24. break-before-make time delay in v out adg1212 adg1211 v in v in v out off v out on q inj = c l v out sd v dd v ss v dd v ss v s r s gnd c l 1nf 04778-025 figure 25. charge injection
adg1211/adg1212/adg1213 rev. a | page 13 of 16 v out 50 network analyzer r l 50 in v in s d 50 off isolation = 20 log v out v s v s v dd v ss 0.1 f v dd 0.1 f v ss gnd 04778-026 figure 26. off isolation channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50 r 50 v s v s v dd v ss 0.1 f v dd 0.1 f v ss 04778-027 figure 27. channel-to-channel crosstalk v out 50 network analyzer r l 50 in v in s d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1 f v dd 0.1 f v ss gnd 04778-028 figure 28. bandwidth v out r s audio precision r l 10k in v in s d v s v p-p v dd v ss 0.1 f v dd 0.1 f v ss gnd 04778-032 figure 29. thd + noise
adg1211/adg1212/adg1213 rev. a | page 14 of 16 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 30. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicato r 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 31. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-3) dimensions shown in millimeters
adg1211/adg1212/adg1213 rev. a | page 15 of 16 ordering guide model temperature range package description package option adg1211yruz 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1211yruz-reel 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1211yruz-reel7 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1211ycpz-500rl7 1 ?40c to +125c lead frame chip scale package (lfcsp_vq) cp-16-3 adg1211ycpz-reel7 1 ?40c to +125c lead frame chip scale package (lfcsp_vq) cp-16-3 adg1212yruz 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1212yruz-reel 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1212yruz-reel7 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1212ycpz-500rl7 1 ?40c to +125c lead frame chip scale package (lfcsp_vq) cp-16-3 adg1212ycpz-reel7 1 ?40c to +125c lead frame chip scale package (lfcsp_vq) cp-16-3 ADG1213YRUZ 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 ADG1213YRUZ-reel 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 ADG1213YRUZ-reel7 1 ?40c to +125c thin shrink sm all outline package (tssop) ru-16 adg1213ycpz-500rl7 1 ?40c to +125c lead frame chip scale package (lfcsp_vq) cp-16-3 adg1213ycpz-reel7 1 ?40c to +125c lead frame chip scale package (lfcsp_vq) cp-16-3 1 z = rohs compliant part.
adg1211/adg1212/adg1213 rev. a | page 16 of 16 notes ?2005C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04778C0C2/09(a)

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